Fanout Design Guide for OSM-S Modules

Designing the carrier board for a solder-down System on Module can look daunting. Our byteENGINE STM32MP2 for example packs a large pad array into a compact OSM-S footprint, and turning that dense grid into clean, manufacturable routing is what makes many engineers hesitate before they start.

The good news is that the fanout is very manageable once you work in the right order. Below is the workflow our team uses, illustrated with a real example carrier board.

Seven steps to a clean fanout

Define the stack-up. Decide how many layers the board has and what the purpose of each is. This is the foundation everything else sits on.
Set-up the design rules. Minimum trace widths and clearances, via and drill sizes, and the rules for impedance-controlled signals. These early choices drive both routing quality and manufacturability.
Route ground and power first. Place vias so they create routing channels instead of blocking other signals, reuse those channels later across layers, and keep the ground planes continuous and avoid split-planes.
Plan the reference and signal layers. Every impedance-controlled signal needs a stable reference plane beside it. In the example stack-up below, signals are routed on TOP, L03 and BOTTOM, while L02 and L05 are reference layers. The middle layer, L03, relies on L04 for its reference.
Route the high-speed signals first. Route the impedance-controlled signals and high-speed interfaces first so the critical signals get the best signal integrity.
Route the low-speed signals next. With the fast signals locked in, the remaining interfaces fall into place around them.
Keep it manufacturable. Avoid microvias, no structures smaller than 0.1 mm, use standard processes only. This results in a cheaper, more reliable and faster production.

The example carrier board

To show the workflow in practice, our example board integrates a broad mix of interfaces: Ethernet, LVDS, DSI, CSI, SPI, SAI, MMC, UART, GPIO and ADC.

Stack-up and impedance profiles

From the stack-up we can derive the impedance profiles the board needs. In this example, three impedances are required: 50 Ohm single-ended, 90 Ohm differential pairs, and 100 Ohm differential pairs.

Figure 2: The six layer stack-up used for the example board.

PCB Layer	Assignment
TOP	Components, signal routing, GND
L02	GND reference for TOP and L03
L03	Signal routing
L04	Power routing, GND reference for L03
L05	GND reference for BOTTOM
BOTTOM	Signal routing

The design rules were kept deliberately standard: through vias with a 0.25 mm hole and 0.5 mm diameter, clearances and trace widths of at least 0.1 mm, no microvias, as well as return-path rules for each impedance profile.

Start with the ground vias

The fanout begins with the ground vias. Placing them centered between the OSM pads keeps the routing channels for the other layers open, which pays off through the rest of the design.

Figure 3: A ground via positioned centrally between the surrounding pads.

The finished result

With ground, power and all signals routed, here is the completed fanout. The impedance-controlled signals were placed first and grouped by profile, and the whole board stays within standard manufacturing limits.

Figure 4: The completed fanout shown across all layers.

Figure 5: The same board with the impedance-controlled signals highlighted.

Conclusion

A clean fanout is less about luck and more about order.
Fix the stack-up and design rules first, route ground and power before anything else, give every fast signal a solid reference, and even a densely packed OSM-S module like the byteENGINE STM32MP2 becomes straightforward to route and easy to manufacture.